1. Field of the Invention
The invention relates to automated design verification techniques for integrated circuits, more particularly to hierarchical device extraction.
2. Description of Background Art
Many structures and systems are comprised of components whose interrelations are defined by design rules. Such structures are often designed using automated design techniques that use symbolic representations of the structure and its elements. An example of such a structure is an integrated circuit.
The physical design of an integrated circuit is frequently described in terms of the symbolic layout of the circuit, rather than the actual geometry of the masks and layers that comprise the chip. When creating mask works for integrated circuits, designers typically begin with a circuit schematic that includes an interconnected network of logic or circuit elements. One or more circuit elements can be combined to form a device. A library of mask work patterns or "cells" that correspond to the various circuit devices used in the design is available to the circuit designer. The designer can thus work with symbolic representations of transistors, wires, and other primitive components, and groups of these components to form a device. These symbolic representations provide a higher level of abstraction than the mask layout. Working at a higher level of abstraction simplifies the design task by allowing the designer to concentrate on designing with higher level devices instead of designing with the low level circuit elements. The use of a symbolic representation allows the designer to simulate and verify the logical operation of the circuit before actual fabrication.
A symbolic layout containing only primitive symbols, i.e. symbols representing transistors, wires, capacitors and other physical components, is termed a "leaf cell." The connections between cells are called "ports." Many layouts contain a large number of substantially identical groups of components or devices. Such a group of components define a cell. The description of the layout can be simplified by treating each group of components as an instance of the particular cell. Each cell is represented symbolically. For example, a cell can be represented as a rectangle with various ports for connecting wires or for abutment with ports of adjacent cells that are similarly represented. The components of the overall layout may consist of many cells, and the layout represents their relative placement and interconnection. Describing the layout in terms of cells rather than primitive symbols further simplifies the task of the designer.
The process of grouping elements and cells may be repeated so that a symbolic layout can be treated as a hierarchical structure with multiple levels. Each level is a symbolic layout of cells and primitive components. Each cell is in turn a symbolic layout of sub-cells and primitive components. The sub-cells and primitive components of a "parent" cell comprise the next lower level in the hierarchy. Since there may be more than one type of cell at any given level, the next lower level may contain several different branches. The cells at the lowest level are leaf cells since they contain no sub-cells, only primitive components, as described above. Cells at any other level are "hierarchy cells." The hierarchy can be visualized as an inverted "tree" with branches extending downward, and the lowest level depends on the branch in which it is located. The leaf cells are at the ends of the branches, and the trunk of the tree represents the symbolic layout of the whole chip, which is often termed the "root cell." This hierarchical description is a natural and concise representation for large designs.
Once the symbolic layout is designed it is tested to verify its logical functioning. Any defective operation is remedied by design changes and the modified design is re-verified. When verifying an integrated circuit design, each device in the design must be extracted, i.e., located and identified. The interconnections between the devices are then checked, and place and routing designs are then verified.
A device is a combination of components that perform a particular function. Device extraction is the process of locating devices within the integrated circuit design. Conventional verification systems require all of the device components to be wholly contained within one cell in order to be identified. In order to verify an integrated circuit design that contains cells in a hierarchical format, the cell must be leveled before device extraction can begin. Leveling occurs because a device design cannot be extracted if it is located in multiple cells. As integrated circuit designs become more complicated design conventional design verification tools requires an inordinate amount of time to verify an integrated circuit design because of the large number of devices.
What is needed is a system and method for extracting a device from a circuit design in which the cells are not leveled for each device that is contained in two or more cells of the cell hierarchy.